Digital demodulator for a frequency modulated signal and an amplitude modulated signal

ABSTRACT

A DMUX 11 outputs data in a digital FM signal in a circulation to produce signals S1 to S4. An MUX 14 alternately outputs inverted signals of the signals S1 and S3, obtaining a signal Si.sub.(k). An MUX 15 alternately outputs inverted signals of the signals S2 and S4, obtaining a signal Sq.sub.(k). An interpolation circuit 17 inserts data having a value of zero between individual data in the output signal of the MUX 14, and cuts off the high-frequency component of the resultant signal, obtaining a signal Si.sub.(i). A second interpolation circuit 19 inserts data having a value of zero between individual data in the output signal of the MUX 15, and cuts off the high-frequency component of the resultant signal, obtaining a signal Sq.sub.(i). An arithmetic operation circuit 2 computes SI.sub.(i-1) ·SQ.sub.(i) -SI.sub.(i) ·Sq.sub.(i-1), and integrates it to obtain a digital demodulated signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital demodulator with a simplestructure, which is capable of obtaining high quality demodulatedsignals.

2. Description of the Related Art

Digital FM demodulators are widely used in the fields of radiocommunications, particularly, in the field of mobile radiocommunications. As digital FM demodulators have more complex structuresthan analog FM demodulators, it is difficult to realize each digital FMdemodulator by an integrated circuit (hereinafter called "IC"), adigital signal processor (hereinafter called "DSP") or the like. This isbecause the function of an ordinary digital FM demodulator needscomplicated processing which involves trigonometric functions or isexecuted by a 90° phase shifter, and thus requires large-capacity memoryand vast amount of computations.

Digital FM demodulators which use a 90° phase shifter are disclosed in,for example, U.S. Pat. No. 4,755,761 and Unexamined Japanese PatentPublication Nos. Sho 63-288504 and Hei 6-291553.

This type of digital FM demodulator suffers a difficulty in reproducingcarriers and a difficulty in being designed into an IC because of theuse of the 90° phase shifter.

SUMMARY OF THE INVENTION

Accordingly, it is an objective of the present invention to provide adigital demodulator with a simple structure.

It is another objective of this invention to provide a digitaldemodulator which can be accomplished by an IC, a DSP or the like.

To achieve the foregoing and other objects, a digital demodulatoraccording to the first aspect of this invention comprises:

time sequential signal generating means for receiving a digital signaland producing a first signal, which includes a sequence of odd-numbereddata in the received digital signal and whose sign is inverted data bydata, and a second signal, which includes a sequence of even-numbereddata in the received digital signal and whose sign is inverted data bydata;

first interpolation means for inserting data having a value of zerobetween individual pieces of data of the first signal output from thetime sequential signal generating means;

second interpolation means for inserting a signal having a value of zerobetween individual pieces of data of the second signal output from thetime sequential signal generating means; and

arithmetic operation means for producing a digital demodulated signalfrom output signals of the first interpolation means and the secondinterpolation means.

A digital demodulator according to the second aspect of this inventioncomprises:

first means for producing digital signals Si.sub.(k) and Sq.sub.(k)respectively expressed by equations (2) and (3) from a digital signalS.sub.(i) expressed by an equation (1);

second means for producing digital signals Si'.sub.(i) and Sq'.sub.(i)respectively expressed by equations (4) and (5) from the digital signalsSi.sub.(k) and Sq.sub.(k) ;

third means for producing digital signals SI.sub.(i) and SQ.sub.(i)respectively expressed by equations (6) and (7) from the digital signalsSi'.sub.(i) and Sq'.sub.(i) ; and

fourth means for producing a digital demodulated signal y.sub.(i)expressed by an equation (8) from the digital signals SI.sub.(i) andSQ.sub.(i) ;

    S.sub.(i) =A·sin (2·π·fc·i/fs+δ·sin (2·π·f·i/fs))               (1)

where A is an amplitude, δ=fd/f, fd is a maximum frequency deviation, fis a frequency of a modulated signal, fs is a sampling frequency, i=1,2, 3, . . . , and fc is a carrier frequency and fc=fs/4,

    Si.sub.(k) =A.sub.(2·k-1) ·cos (δ·sin (2·π·f·(2·k-1)/fs)) (k=1, 2, 3, . . . )                                                       (2)

    Sq.sub.(k) =A.sub.(2·k) ·sin (δ·sin (4·π·f·k/fs))               (3)

    Si'.sub.(i) ={A.sub.(1) ·cos (δ·sin (2·π·f/fs)), 0, A.sub.(3) ·cos (δ·sin (6·π·f/fs)), 0, . . . ,}(4)

    Sq'.sub.(i) ={0, A.sub.(2) ·sin (δ·sin (4·π·f/fs)), 0, A.sub.(4) ·sin (δ·sin (8·π·f/fs)), . . . ,}(5)

    SI.sub.(i) =A.sub.(i) ·cos (δ·sin (2·π·f·i/fs))               (6)

    SQ.sub.(i) =A.sub.(i) ·sin (δ·sin (2·π·f·i/fs))               (7)

    y.sub.(i) =B·{sin (2·π·f·i/fs)-sin (2·π·f·(i-1)/fs)}           (8)

where B is approximately constant.

A digital demodulator according to the third aspect of this inventioncomprises:

first means for producing digital signals Si.sub.(k) and Sq.sub.(k)respectively expressed by equations (10) and (11) from a digital signalS.sub.(i) expressed by an equation (9);

second means for producing digital signals Si'.sub.(k) and Sq'.sub.(k)respectively expressed by equations (12) and (13) from the digitalsignals Si.sub.(k) and Sq.sub.(k) ;

third means for producing digital signals SI.sub.(i) and SQ.sub.(i)respectively expressed by equations (14) and (15) from the digitalsignals Si'.sub.(k) and Sq'.sub.(k) ; and

fourth means for producing a digital demodulated signal y.sub.(i)expressed by an equation (16) from the digital signals SI.sub.(i) andSQ.sub.(i) ;

    S.sub.(i) =(A+1)·cos (2·π·fc·t/fs)(9)

where A is an amplitude signal, fc is a carrier frequency, and fs is asampling frequency,

    Si.sub.(k) =(A.sub.(2·k-1) +1)·sin (2·(2·k-1)·π·Δf+φ)) (k=1, 2, 3, . . . )                                             (10)

    Sq.sub.(k) =(A.sub.(2·k) +1)·cos (4·k·π·Δf+φ))     (11)

    {Si'.sub.(k) }={(A.sub.(i) +1)·sin (2·π·Δf+φ), 0, (A.sub.(3) +1)·sin (6·π·Δf+φ), 0 , . . . ,}   (12)

    {Sq'.sub.(k) }={0, (A.sub.(2) +1)·cos (4·π·Δf+φ), 0, (A.sub.(4) +1)·sin (8·π·Δf+φ), 0 , . . . ,}   (13)

    SI.sub.(i) =(A.sub.(i) +1)·sin (2·π·Δf+φ)                 (14)

    SQ.sub.(i) =(A.sub.(i) +1)·cos (2·π·Δf+φ)                 (15)

    y.sub.(i) =B·(A.sub.(i) +1).sup.2                 ( 16)

where B is approximately constant.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the structure of an FM receiveraccording to the first embodiment of the present invention;

FIG. 2 is a block diagram showing the structure of an interpolationcircuit shown in FIG. 1;

FIG. 3 is a block diagram showing the structure of an FM receiveraccording to the second embodiment of the present invention;

FIG. 4 is a block diagram showing the structure of an AM receiveraccording to the third embodiment of the present invention;

FIG. 5 is a block diagram showing the structure of a digital FMdemodulator embodying this invention, which is constituted by using aDSP;

FIG. 6 is a spectrum distribution diagram for an FM signal used inevaluating the digital demodulator having the structure shown in FIG. 5;

FIG. 7 is a spectrum distribution diagram for an FM demodulated signalused in evaluating the digital demodulator having the structure shown inFIG. 5;

FIG. 8 is a graph showing the relationship between the frequency of ademodulated signal and demodulation distortion; and

FIG. 9 is a block diagram showing a modification of a circuit forproducing a time sequential signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Digital FM demodulators according to preferred embodiments of thepresent invention will now be described with reference to theaccompanying drawings.

First Embodiment

FIG. 1 is a block diagram showing the structure of an FM receiver 1according to the first embodiment of the present invention.

As illustrated, this FM receiver 1 comprises an antenna 3, a receivingcircuit 4, a sampling circuit 5, an oscillator 6, and a digital FMdemodulator 2.

The digital FM demodulator 2 includes a demultiplexer (DMUX) 11,inverters 12 and 13, multiplexers (MUX) 14 and 15, interpolationcircuits 17 and 19, and an arithmetic operation circuit 21. Thearithmetic operation circuit 21 includes delay elements 22 and 23,multipliers 27 and 29 and a subtracter 33.

The antenna 3 supplies an FM signal Sa to the receiving circuit 4. Thereceiving circuit 4 performs amplification, frequency conversion, tuningand the like on the received FM signal Sa to produce an intermediatefrequency signal S.sub.(t), and supplies the intermediate frequencysignal S.sub.(t) to the sampling circuit 5. The sampling circuit 5samples the intermediate frequency signal S.sub.(t) to convert it to adigital signal S.sub.(i) in accordance with a sampling signal suppliedfrom the oscillator 6, and supplies the digital signal S.sub.(i) to thedigital FM demodulator 2. The oscillator 6 supplies a sampling signal ofa sufficiently higher frequency than that of a demodulated signal to thesampling circuit 5 and the digital FM demodulator 2.

The DMUX 11 sequentially outputs the input signal (data) supplied fromthe sampling circuit 5 to four output terminals as signals S1 to S4. Theinverters 12 and 13 perform phase conversion of 180 degrees (signinversion) on the signals S3 and S4 supplied from the third and fourthoutput terminals, respectively. The MUX 14 alternately selects andoutputs the signals supplied from the first output terminal of the DMUX11 and from the inverter 12. The MUX 15 alternately selects and outputsthe signals supplied from the second output terminal of the DMUX 11 andfrom the inverter 13.

Each of the interpolation circuits 17 and 19 comprises a zero insertingcircuit 41 and an LPF (Low-Pass Filter) 42, as shown in FIG. 2. The zeroinserting circuit 41 inserts a signal (data) of a value of zero (0)between signals (data) which are sequentially output from the MUX 14 or15. The LPF 42 removes the high-frequency component from the signalsupplied from the zero inserting circuit 41.

The delay elements 22 and 23 of the arithmetic operation circuit 21respectively delay the output signals the interpolation circuits 17 and19 by one sampling period.

The multiplier 27 multiplies the output signal of the delay element 22by the output signal of the interpolation circuit 19.

The multiplier 29 multiplies the output signal of the delay element 23by the output signal of the interpolation circuit 17.

The subtracter 33 subtracts the output signal of the multiplier 27 fromthe output signal of the multiplier 29.

The operation of the FM receiver 1 shown in FIG. 1 will now bedescribed.

The digital FM demodulator 2 receives the intermediate frequency signalS.sub.(t), which has been sampled by the sampling circuit 5 and isexpressed by an equation (17). For easier understanding, the amplitude Aof the intermediate frequency signal S.sub.(t) is assumed to be aconstant value Im.

    S.sub.(t) =Im·sin (2·π·fc·t+δ·sin (2·π·f·t))                  (17)

where fc is the carrier frequency, δ=fd/f, fd is the maximum frequencydeviation, f is the frequency of a modulated signal, fs is the samplingfrequency, and i=1, 2, 3, . . .

When the carrier frequency fc is set to 1/4 of the sampling frequency fs(fc=fs/4), the equation (17) can be rewritten as an equation (18).

That is, a digital FM signal S.sub.(i) expressed by the equation (18) issupplied to the digital FM demodulator 2.

    S.sub.(i) =Im·sin ((π·i)/2+δ·sin (2·πf·i/fs))                         (18)

The signal S.sub.(i) given by the equation (18) can be rewritten asexpressed by an equation (19). ##EQU1##

The DMUX 11 sequentially outputs the individual pieces of data of thedigital signal Si.sub.(i) expressed by the equation (19) to the fouroutput terminals in circulation. Therefore, the digital signalsS1.sub.(k) to S4.sub.(k) to be output from the first to fourth outputterminals are expressed by the following equations (20) to (23).

    S1.sub.(k) =Im·cos (δ·sin (2·π·f·(4·k-3)/fs))(20)

    S2.sub.(k) =-Im·sin (δ·sin (2·π·f·(4·k-2)/fs))(21)

    S3.sub.(k) =-Im·cos (δ·sin (2·π·f·(4·k-1)/fs))(22)

    S4.sub.(k) =Im·sin (δ·sin (8·π·f·k/fs))               (23)

The inverter 12 performs phase conversion of 180 degrees (signinversion) on the signal S3.sub.(k) to obtain -S3.sub.(k), which is inturn supplied to the MUX 14. The MUX 14 receives the signal S1.sub.(k)and -S3.sub.(k) and alternately outputs the input signals. The outputsignal Si.sub.(k) of the MUX 14 or the digital signal output from theMUX 14 is given by an equation (24). This digital signal Si.sub.(k)consists of a sequence of odd-numbered data in the digital FM signalS.sub.(i), and its sign inverts data by data.

The inverter 13 performs phase conversion of 180 degrees (signinversion) on the signal S4.sub.(k) to obtain -S4.sub.(k), which is inturn supplied to the MUX 15. The MUX 15 receives the signal S2.sub.(k)and -S4.sub.(k) and alternately outputs the input signals. The digitalsignal Sq.sub.(k) output from the MUX 15 is given by an equation (25).This output signal Sq.sub.(k) consists of a sequence of even-numbereddata in the digital FM signal S.sub.(i), and its sign inverts data bydata. ##EQU2## where k=1, 2, 3, . . .

The signals Si.sub.(k) and Sq.sub.(k) have the relationship given by anequation (26).

    Si.sub.(k+1) = Sq.sub.(k)                                  (26)

where Sq.sub.(k) indicates that it has a phase difference of 90 degreesto Sq.sub.(k).

To convert the sampling frequency of Si.sub.(k) and Sq.sub.(k) to fs,the zero inserting circuit 41 of the interpolation circuit 17 receivesthe signal Si.sub.(k), inserts data of a value of zero (0) betweenindividual data of the signal Si.sub.(k) and outputs a signalSi'.sub.(i) given by an equation (27)

The zero inserting circuit 41 of the interpolation circuit 19 receivesthe signal Sq.sub.(k), inserts data of a value of zero (0) betweenindividual data of the signal Sq.sub.(k), and outputs a signalSq'.sub.(i) given by an equation (28).

    Si'.sub.(i) ={S.sub.(1), 0, -S.sub.(3), 0, S.sub.(5), 0, -S.sub.(7), . . . }(27)

    Sq'.sub.(i) ={0,S.sub.(2), 0, -S.sub.(4), 0, S.sub.(6), 0,-S.sub.(8), . . . }                                                         (28)

The LPF 42 of the interpolation circuit 17 removes the high-frequencycomponent of the signal Si'.sub.(i) and outputs a digital signalSI.sub.(i) given by an equation (29). The LPF 42 of the interpolationcircuit 19 removes the high-frequency component of the signalSq'.sub.(i) and outputs a digital signal SQ.sub.(i) given by an equation(30).

    SI.sub.(i) =Im·cos (δ·sin (2·π·f·i/fs))               (29)

    SQ.sub.(i) =Im·sin (δ·sin (2·π·f·i/fs))               (30)

The signals SI.sub.(i) and SQ.sub.(i) are orthogonal to each other asindicated by an equation (31).

    SI.sub.(i) = SQ.sub.(i)                                    (31)

The delay element 22 delays the signal SI.sub.(i) by one sampling periodand outputs a signal SI.sub.(i-1). The multiplier 27 multiplies thesignal SI.sub.(i-1) by the output signal SQ.sub.(i) of the interpolationcircuit 19. The delay element 23 delays the signal SQ.sub.(i) by onesampling period and outputs a signal SQ.sub.(i-1). The multiplier 29multiplies the signal SQ.sub.(i-1) by the output signal SI.sub.(i) ofthe interpolation circuit 17. The subtracter 33 subtracts the outputsignal of the multiplier 27 from the output signal of the multiplier 29,and outputs a digital signal Y.sub.(i) expressed by an equation (32).##EQU3##

The sampling frequency fs is set sufficiently higher than the frequencyf of a demodulated signal as mentioned above, so that the equation (32)can be rewritten as the following equation (33).

    Y.sub.(i) ≈Im.sup.2 ·δ(sin (2·π·f·i/fs)-sin (2·π·f·(i-1)/fs))           (33)

The demodulated signal may be obtained by integrating the signalY.sub.(i) given by the equation (33).

The digital FM demodulator 2 in FIG. 2 can demodulate an FM input signalwith a constant amplitude. Further, since there are only two LPFs used,one in each of the interpolation circuits 17 and 19, this digital FMdemodulator can be realized by a simple and small-scale circuitstructure. The digital FM demodulator 2 can easily be constituted of anintegrated circuit such as IC or DSP.

Second Embodiment

Although the foregoing description of the digital FM demodulator 2according to the first embodiment has been given with reference to thecase where the amplitude A of the intermediate frequency signalS.sub.(t) takes a constant value Im, the digital FM demodulator 2 ofthis invention may be adapted to the case where the amplitude of theinput signal S.sub.(t) is not constant. The following will discuss thestructure and operation of the digital FM demodulator 2 according to thesecond embodiment, which is adapted to the case where it can demodulatethe input FM signal even when the amplitude A of the intermediatefrequency signal S.sub.(t) is not constant.

FIG. 3 shows the structure of the FM receiver 1 according to the secondembodiment. The structure of this FM receiver 1 is basically the same asthe one shown in FIG. 1, except for the structure of the arithmeticoperation circuit 21.

The arithmetic operation circuit 21 in this embodiment comprises delayelements 22 and 23, multipliers 25, 27, 29 and 31, a subtracter 33, anadder 35, and a divider 37.

The multipliers 25 and 31 each obtain the square of the same signal. Theadder 35 adds the output signals of the multipliers 25 and 31. Thedivider 37 divides the output signal of the subtracter 33 by the outputsignal of the adder 35. The delay elements 22 and 23, the multipliers 27and 29 and the subtracter 33 have the same functions as those of thefirst embodiment.

An analog FM signal S.sub.(t) including amplitude information isexpressed by an equation (34).

    S.sub.(t) =A.sub.(t) ·sin (2·π·fc·t+δ·sin (2·π·f·t))                  (34)

The sampling circuit 5 samples the analog FM signal S.sub.(t) inaccordance with the sampling signal and performs A/D conversion on theresultant signal to obtain a digital FM signal S.sub.(i) expressed by anequation (35).

    S.sub.(i) =A.sub.(i) ·sin ((π·i)/2+δ·sin (2·π·f.multidot.i/fs))                                                (35)

The DMUX 11 sequentially outputs the individual signal components of thedigital FM signal S.sub.(i) to the four output terminals to producesignals S1.sub.(k) to S4.sub.(k) expressed by the following equations(36) to (39). The carrier frequency fc and the sampling frequency fshave the relationship of fc=fs/4.

    S1.sub.(k) =A.sub.(4·k-3) ·cos (δ·sin (2·π·f·(4·k-3)/fs))(36)

    S2.sub.(k) =-A.sub.(4·k-2) ·sin (δ·sin (2·π·f·(4·k-2)/fs))(37)

    S3.sub.(k) =A.sub.(4·k-1) ·cos (δ·sin (2·π·f·(4·k-1)/fs))(38)

    S4.sub.(k) =A.sub.(4·k) ·sin (δ·sin (8·π·f·k/fs))               (39)

where k=1, 2, 3, . . .

The inverter 12 performs phase conversion of 180 degrees (signinversion) on the signal S3.sub.(k) to obtain -S3.sub.(k), which is inturn supplied to the MUX 14. The MUX 14 receives the signal S1.sub.(k)and -S3.sub.(k) and alternately outputs the input signals, obtaining asignal Si.sub.(k) expressed by an equation (40).

The inverter 13 performs phase conversion of 180 degrees (signinversion) on the signal S4.sub.(k) to obtain -S4.sub.(k), which is inturn supplied to the MUX 15. The MUX 15 receives the signal S2.sub.(k)and -S4.sub.(k) and alternately outputs the input signals, obtaining asignal Sq.sub.(k) expressed by an equation (41).

    Si.sub.(k) =A.sub.(2·k-1) ·cos (δ·sin (2·π·f·(2·k-1)/fs))(40)

    Sq.sub.(k) =A.sub.(2·k) ·sin (δ·sin (4·π·f·k/fs))               (41)

The zero inserting circuit 41 of the interpolation circuit 17 receivesthe signal Si.sub.(k), inserts data of a value of zero (0) betweenindividual signal components, and outputs a signal Si'.sub.(i) given byan equation (42).

The zero inserting circuit 41 of the interpolation circuit 19 receivesthe signal Sq.sub.(k), inserts data of a value of zero (0) betweenindividual signal components, and outputs a signal Sq'.sub.(i) given byan equation (43). ##EQU4##

The LPF 42 of the interpolation circuit 17 removes the high-frequencycomponent of the signal Si'.sub.(i) and outputs a digital signalSI.sub.(i) given by an equation (44). The LPF 42 of the interpolationcircuit 19 removes the high-frequency component of the signalSq'.sub.(i) and outputs a digital signal SQ.sub.(i) given by an equation(45).

    SI.sub.(i) =A.sub.(i) ·cos (δ·sin (2·π·f·i/fs))               (44)

    SQ.sub.(i) =A.sub.(i) ·sin (δ·sin (2·π·f·i/fs))               (45)

The signals SI.sub.(i) and SQ.sub.(i) are orthogonal to each other asindicated by an equation (46).

    SI.sub.(i) = SQ.sub.(i)                                    (46)

Next, the multiplier 25 squares the signal SI.sub.(i) to obtain a signalSI².sub.(i). The multiplier 31 squares the signal SQ.sub.(i) to obtain asignal SQ².sub.(i). The adder 35 adds the signal SI².sub.(i) and thesignal SQ².sub.(i) to obtain a signal A².sub.(2) expressed by anequation (47).

    A.sup.2.sub.(i) =SI.sup.2.sub.(i) +SQ.sup.2.sub.(i)        (47)

The delay element 22 delays the signal SI.sub.(i) by one sampling periodand outputs a signal SI.sub.(i-1). The multiplier 27 multiplies thesignal SI.sub.(i-1) by the output signal SQ.sub.(i) of the interpolationcircuit 19. The delay element 23 delays the signal SQ.sub.(i) by onesampling period and outputs a signal SQ.sub.(i-1). The multiplier 29multiplies the signal SQ.sub.(i-1) by the output signal SI.sub.(i) ofthe interpolation circuit 17. The subtracter 33 subtracts the outputsignal of the multiplier 27 from the output signal of the multiplier 29,and outputs a digital signal Y.sub.(i) expressed by an equation (48).##EQU5##

The divider 37 divides the digital signal Y.sub.(i) given by theequation (48) by the signal A2.sub.(i) given by the equation (47) andoutputs a signal Y.sub.(i) /A².sub.(i).

    Y.sub.(i) /A.sup.2.sub.(i) =A.sub.(i-1) ·sin (δ·(sin (2·π·f·i/fs)-sin (2·π·f·(i-1)/fs))/A(i)      (49)

Because the sampling frequency fs is sufficiently higher than thefrequency f of the demodulated signal, an equation (50) is satisfied.Substituting the equation (50) into the equation (49) obtains anequation (51).

    A.sub.(i-1) /A.sub.(i) ≈1                          (50)

    Y.sub.(i) /A.sup.2.sub.(i) ≈sin (δ·(sin (2·π·f·i/fs))-sin (2·π·f·(i-1)/fs)))          (51)

Because the sampling frequency fs is sufficiently higher than thefrequency f of the demodulated signal, the equation (51) can berewritten as an equation (52).

    Y.sub.(i) /A.sup.2.sub.(i) ≈δ·(sin (2·π·f·i/fs)-sin (2·π·f·(i-1)/fs))           (52)

The demodulated signal may be obtained by integrating the signalY.sub.(i) /A².sub.(i) given by the equation (51) or the equation (52).

In the equations (51) and (52), the amplitude A.sub.(t) is canceled.That is, the demodulated signal can be obtained even if the amplitudeinformation may be canceled. Even if an FM signal containing amplitudeinformation is input, therefore, the digital FM demodulator 2 accordingto the second embodiment can still obtain the demodulated signalproperly.

Although the foregoing description has been given on the assumption thatfc=fs/4 is satisfied, the demodulation is still possible even when thecarrier frequency fc is shifted from fs/4 as indicated by an equation(53).

    fc=fs/4±Δf 0<Δf<fs/4                        (53)

In this case, the equation (52) can be rewritten as an equation (54).##EQU6##

Because the sampling frequency fs is set sufficiently higher than thefrequency f of the demodulated signal, the equation (54) can berewritten as an equation (55).

    Y.sub.(i) /A.sup.2.sub.(i) ≈δcos (2·π·Δf/fs) (sin (2·π·f·i/fs))-sin (2·πf·(i-1)/fs)±δ·sin (2·π·Δf/fs)                    (55)

As is apparent from the equation (55), the DC (Direct Current) biasincreases and the amplitude of the demodulated signal decreases as Δfincreases, but the tuning characteristic is substantially the same asthat of an ordinary analog FM demodulator.

The digital FM demodulator 2 of this embodiment has only one LPFprovided in each of the interpolation circuits 17 and 19. Therefore, thenumber of required LPFs can be minimized so that a digital FMdemodulator with a simple and small-scale circuit structure can beprovided. The digital FM demodulator 2 can easily be constituted of anintegrated circuit such as IC or DSP.

Third Embodiment

While the first and second embodiments in the foregoing description havebeen described as demodulators which demodulate digital FM signals, thisinvention may also adapted to a demodulator which demodulates digital AMsignals.

This type of digital demodulator will now be discussed specifically.

FIG. 4 exemplifies the structure of an AM demodulator. This structure isequivalent to the structure shown in FIG. 3 from which the delayelements 22 and 23, the multipliers 27 and 29, the subtracter 33 and thedivider 37 are removed.

The operation of the AM demodulator with this structure will now bedescribed.

An analog AM signal S.sub.(t) output from the receiving circuit 4 isexpressed by an equation (56).

    S.sub.(t) =A.sub.(t) ·cos (2·π·fc·t+2·π·Δf+φ)+cos (2·π·fc·t+2·π·Δf+φ)                                                     (56)

where A.sub.(t) is an amplitude signal, fc is a carrier frequency, Δf isan unknown frequency deviation and φ is a phase deviation.

When fc=fs/4, the output signal of the sampling circuit 5 is expressedby the following equation (57).

    {S.sub.(i) }={-(A.sub.(1) +1)·sin (2·π·Δf+φ), -(A.sub.(2) +1)·cos (4·π·Δf+φ), (A.sub.(3) +1)·sin (6·π·Δf+φ), (A.sub.(4) +1)·cos (8·π·Δf+φ), . . . }        (57)

The DMUX 11 outputs the individual data of this digital signal from thefour output terminals. The inverters 12 and 13 invert the supplied data.

The MUX 14 alternately selects and outputs the output data S1 and -S3from the DMUX 11. The MUX 15 alternately selects and outputs the outputdata -S2 and S4 from the DMUX 11. The output of the MUX 14 is expressedby an equation (58) and the output of the MUX 15 is expressed by anequation (59).

    Si.sub.(k) =(A.sub.(2·k-1) +1)·sin (2·(2·k-1)·π·Δf+φ)(58)

    Sq.sub.(k) =(A.sub.(2·k) +1)·cos (4·k·π·Δf+φ) (k=1, 2, 3, . . . )(59)

The zero inserting circuit 41 of the interpolation circuit 17 outputs adigital signal Si'.sub.(k) expressed by an equation (60).

The zero inserting circuit 41 of the interpolation circuit 19 outputs adigital signal Sq'.sub.(k) expressed by an equation (61).

    {Si'.sub.(k) }={(A.sub.(1) +1)·sin (2·π·Δf+φ) 0, (A(3)+1)·sin (6·π·Δf+φ), 0, . . . ,}    (60)

    {sq'.sub.(k) }={0, (A.sub.(2) +1)·cos (4·π·Δf+φ), 0, (A.sub.(4) +1)·sin (8·π·Δf+φ), 0, . . . ,}    (61)

The LPF 42 of the interpolation circuit 17 removes the high-frequencycomponent from the digital signal Si'.sub.(k) given by the equation (60)and outputs a digital signal SI.sub.(i) expressed by an equation (62).

The LPF 42 of the interpolation circuit 19 removes the high-frequencycomponent from the digital signal Sq'.sub.(k) given by the equation (61)and outputs a digital signal SQ.sub.(i) expressed by an equation (63).

    SI.sub.(i) =(A.sub.(i) +1)·sin (2·π·Δf+φ)                 (62)

    SQ.sub.(i) =(A.sub.(i) +1)·cos (2·π·Δf+φ)                 (63)

The multiplier 25 obtains the square of the output signal SI.sub.(i) ofthe interpolation circuit 17. The multiplier 31 obtains the square ofthe output signal SQ.sub.(i) of the interpolation circuit 19.

The adder 35 adds the digital signals output from the multipliers 25 and31, and outputs a digital demodulated signal expressed by an equation(64).

    y.sub.(i) =I.sup.2.sub.(i) +SQ.sup.2.sub.(i) =(A.sub.(i) +1).sup.2(64)

An analog demodulated signal is obtained by D/A conversion of thisdemodulated signal y.sub.(i).

Fourth Embodiment

FIG. 5 exemplifies the system structure in which the receiver 2according to any of the first to third embodiments is accomplished byusing a DSP (Digital Signal Processor).

The output signal of the receiving circuit 4 is supplied to an A/Dconverter 51 for A/D conversion, which serves as the sampling circuit 5.The output signal of the A/D converter 51 is supplied to a DSP 52 whichconstitutes the digital demodulator 2. The digital demodulated signaloutput from the DSP 52 is converted to an analog signal by a D/Aconverter 53. An audio signal output from the D/A converter 53 issupplied to an analog LPF 54 where its high-frequency component isremoved. The resultant signal is supplied via a driving amplifier or thelike to a loudspeaker or the like. The A/D converter 51 is also suppliedwith a sampling clock of a frequency fs from an oscillator 55. Thesampling clock signal is supplied as an operation clock to the DSP 52and the D/A converter 53.

The sampling frequency fs is very high as compared with the frequency ofthe demodulated signal. For an analog demodulator, the samplingfrequency fs is determined by an equation (65) if the maximum frequencydeviation fd of an analog FM signal is set to 5 Hz, the same as that ofan ordinary FM receiver.

    fs/4+15 KHz≦f/2                                     (65)

Thus, the sampling frequency fs is set to fs≧60 Hz. The digital FMdemodulator 2 of this invention was evaluated by using the structureshown in FIG. 5.

First, the specification of the evaluating system will be discussed.

16-bit TMS320C25 of a fixed point type was used as the DSP 52, and thesampling frequency fs was set to 62.5 Hz. The LPFs 42 used in theinterpolation circuits 17 and 19 were constituted one-order low-passfilters having a cutoff frequency of 18 Hz, the maximum frequencydeviation fd of an analog FM signal was set to 5 Hz, and a tone signalof 1 Hz was used as the demodulated signal.

FIGS. 6 and 7 show the spectrum distributions of an FM modulated signaland an FM demodulated signal in this case, respectively. FIG. 8 showsthe demodulation distortion at 300 Hz to 3 Hz. It was confirmed that thedemodulation distortion is extremely small such that the maximumdemodulation distortion for the signal level of 0 dB was -47 dB orsmaller.

It is apparent from this evaluation result that the FM demodulator 2according to the above-described embodiments, though having a relativelysimple structure, can obtain high-quality demodulated signals.

This invention is not limited to the above-described embodiments, butmay be modified and adapted in various other forms.

For instance, although the signals S3.sub.(k) and S4.sub.(k) in theoutput signal of the DMUX 11 are respectively input to the inverters 12and 13 to accomplish phase conversion of 180 degrees (sign inversion) inthe structures in FIGS. 1 and 3, the signals S2.sub.(k) and S3.sub.(k)may be input to those inverters, i.e., one of the signals S1.sub.(k) andS3.sub.(k) and one of the signals S2.sub.(k) and S4.sub.(k) may be inputto the inverters for phase conversion.

Although the signals S2.sub.(k) and S3.sub.(k) in the output signal ofthe DMUX 11 are respectively input to the inverters 12 and 13 toaccomplish phase conversion of 180 degrees (sign inversion) in thestructure in FIG. 4, the signals S3.sub.(k) and S4.sub.(k) may be inputto those inverters, i.e., one of the signals S1.sub.(k) and S3.sub.(k)and one of the signals S2.sub.(k) and S4.sub.(k) may be input to theinverters for phase conversion.

Although the demultiplexer and multiplexer are used to produce thesignals Si.sub.(k) and Sq.sub.(k) in the above-described embodiments,any structure may be employed as long as time sequential signals whoseabsolute values are expressed by Si.sub.(k) and Sq.sub.(k) are obtained.For example, the structure in FIG. 9 has a two-output demultiplexer 61which sequentially outputs signals S.sub.(1), S.sub.(3), S.sub.(5), andso forth from one of the output terminals, and sequentially outputssignals S.sub.(2), S.sub.(4), S.sub.(6) and so forth from the otheroutput terminal. Time sequential signals Si.sub.(k) and Sq.sub.(k) canbe produced by directly outputting the signals Si.sub.(1), S.sub.(5) andso forth and the signals S.sub.(2), S.sub.(6) and so forth via buffers62 and 64, and outputting the signals S.sub.(3), S.sub.(7) and so forthand the signals S.sub.(4), S.sub.(8) and so forth after being invertedby respective inverters 63 and 65.

In short, this invention can provide a high-performance digitaldemodulator with a small-scale and simple circuit structure withoutusing a complex circuit like a 90 degree phase shifter or the like whichhas a large amount of hardware.

What is claimed is:
 1. A digital demodulator comprising:time sequentialsignal generating means for receiving a digital signal and producing afirst signal, which includes of a sequence of odd-numbered data in saidreceived digital signal and whose sign is inverted data by data, and asecond signal, which includes a sequence of even-numbered data in saidreceived digital signal and whose sign is inverted data by data; firstinterpolation means for inserting data having a value of zero betweenindividual pieces of data of said first signal output from said timesequential signal generating means; second interpolation means forinserting data having a value of zero between individual pieces of dataof said second signal output from said time sequential signal generatingmeans; and arithmetic operation means for producing a digitaldemodulated signal from output signals of said first interpolation meansand said second interpolation means.
 2. The digital demodulatoraccording to claim 1, wherein said time sequential signal generatingmeans includes:demultiplexer means for receiving a digital receptionsignal and outputting data in said digital reception signal incirculation to thereby convert said digital reception signal to first tofourth time sequential signals; phase conversion means for shifting aphase of one of said first and third time sequential signals and a phaseof one of said second and fourth time sequential signals by 180 degrees;first multiplexer means for receiving the other one of said first andthird sequential signals and said phase-shifted one of said first andthird sequential signals from said phase converting means andalternately and sequentially outputting said received signals; andsecond multiplexer means for receiving the other one of said second andfourth sequential signals and said phase-shifted one of said second andfourth sequential signals from said phase converting means andalternately and sequentially outputting said received signals.
 3. Thedigital demodulator according to claim 1, wherein said arithmeticoperation means includes:first delay means for delaying an output signalof said first interpolation means by one sampling period of said digitalreception signal; second delay means for delaying an output signal ofsaid second interpolation means by one sampling period of said digitalreception signal; first multiplier means for multiplying an outputsignal of said first delay means by an output signal of said secondinterpolation means; second multiplier means for multiplying an outputsignal of said first interpolation means by an output signal of saidsecond delay means; and subtraction means for obtaining a differencebetween an output signal of said second multiplier means and an outputsignal of said first multiplier means.
 4. The digital demodulatoraccording to claim 1, wherein said arithmetic operation meansincludes:first delay means for delaying an output signal of said firstinterpolation means by one sampling period of said digital receptionsignal; second delay means for delaying an output signal of said secondinterpolation means by one sampling period of said digital receptionsignal; first multiplier means for multiplying an output signal of saidfirst delay means by an output signal of said second interpolationmeans; second multiplier means for multiplying an output signal of saidfirst interpolation means by an output signal of said second delaymeans; subtraction means for obtaining a difference between an outputsignal of said second multiplier means and an output signal of saidfirst multiplier means; third multiplier means for obtaining a square ofsaid output signal of said first interpolation means; fourth multipliermeans for obtaining a square of said output signal of said secondinterpolation means; adder means for adding an output signal of saidthird multiplier means and an output signal of said fourth multipliermeans; and divider means for dividing one of an output signal of saidsubtraction means and an output signal of said adder means by the other.5. The digital demodulator according to claim 1, wherein said arithmeticoperation means includes:first square means for obtaining a square ofsaid output signal of said first interpolation means; second squaremeans for obtaining a square of said output signal of said secondinterpolation means; and adder means for adding an output signal of saidfirst square means and an output signal of said second square means. 6.The digital demodulator according to claim 1, wherein each of said firstand second interpolation means includes inserting means for inserting asignal having a value of zero between individual data of said firstsignal and a low-pass filter for removing a high-frequency component ofan output signal of said inserting means.
 7. A digital demodulatorcomprising:first means for producing digital signals Si.sub.(k) andSq.sub.(k) respectively expressed by equations (67) and (68) from adigital signal S.sub.(i) expressed by an equation (66); second means forproducing digital signals Si'.sub.(i) and Sq'.sub.(i) respectivelyexpressed by equations (69) and (70) from said digital signalsSi.sub.(k) and Sq.sub.(k) ; third means for producing digital signalsSI.sub.(i) and SQ.sub.(i) respectively expressed by equations (71) and(72) from said digital signals Si'.sub.(i) and Sq'.sub.(i) ; and fourthmeans for producing a digital demodulated signal y.sub.(i) expressed byan equation (73) from said digital signals SI.sub.(i) and SQ.sub.(i) ;

    S.sub.(i) =A·sin (2·π·fc·i/fs+δ·sin (2·π·f·i/fs)                (66)

where A is an amplitude, δ=fd/f, fd is a maximum frequency deviation, fis a frequency of a modulated signal, fs is a sampling frequency, i=1,2, 3, . . . , and fc is a carrier frequency and fc=fs/4,

    Si.sub.(k) =A.sub.(2·k-1) ·cos (δ·sin (2·π·f·(2·k-1)/fs)) (k=1, 2, 3, . . . )                                                       (67)

    Sq.sub.(k) =A.sub.(2·k) ·sin (δ·sin (4·π·f·k/fs))               (68)

    Si'.sub.(i) ={A.sub.(1) ·cos (δ·sin (2·π·f/fs)), 0, A.sub.(3) ·cos (δ·sin (6·π·f/fs)), 0, . . . ,}(69)

    Sq'.sub.(i) ={0, A.sub.(2) ·sin (δ·sin (4·π·f/fs)), 0, A.sub.(4) ·sin (δ·sin (8·π·f/fs)), . . . ,}(70)

    SI.sub.(i) =A.sub.(i) ·cos (δ·sin (2·π·f·i/fs)                (71)

    SQ.sub.(i) =A.sub.(i) ·sin (δ·sin (2·π·f·i/fs))               (72)

    y.sub.(i) =B·{sin (2·π·f·i/fs)-sin (2·π·f·(i-1)/fs)}           (73)

where B is approximately constant.
 8. The digital demodulator accordingto claim 7, wherein said first means includes:first conversion means forproducing four digital signals S1.sub.(k) to S4.sub.(k), expressed byequations (74) to (77), from a digital FM signal S.sub.(i) expressed bysaid equation (66), and second conversion means for producing saiddigital signals Si.sub.(k) and Sq.sub.(k), expressed by said equations(67) and (68), from said digital signals S1.sub.(k) to S4.sub.(k),

    S1.sub.(k) =A·cos (δ·sin (2·π·f·(4·k-3)/fs))(74)

    S2.sub.(k) =-A·sin (δ·sin (2·π·f·(4·k-2)/fs))(75)

    S3.sub.(k) =-A·cos (δ·sin (2·π·f·(4·k-1)/fs))(76)

    S4.sub.(k) =A·sin (δ·sin (8·π·f·k/fs))               (77).


9. The digital demodulator according to claim 7, wherein said thirdmeans comprises a low-pass filter for removing high-frequency componentsof said signals Si'.sub.(i) and Sq'.sub.(i).
 10. The digital demodulatoraccording to claim 7, wherein said amplitude A is constant; andsaidfourth means includes: first delay means for delaying said signalSI.sub.(1) by a predetermined sampling period to produce a signalSI(_(i-10)) ; second delay means for delaying said signal SQ.sub.(i) bya predetermined sampling period to produce a signal SQ_(i-1)) ; firstmultiplier means for multiplying said signal SQ.sub.(i-1) by said signalSI.sub.(i) ; second multiplier means for multiplying said signalSI.sub.(i-1) by said signal SQ.sub.(i) ; subtraction means for obtaininga difference between an output signal of said first multiplier means andan output signal of said second multiplier means.
 11. The digitaldemodulator according to claim 7, wherein said fourth meansincludes:first delay means for delaying said signal SI.sub.(i) by apredetermined sampling period to produce a signal SI.sub.(i-1) ; seconddelay means for delaying said signal SQ.sub.(i) by a predeterminedsampling period to produce a signal SQ.sub.(i-1) ; first multipliermeans for multiplying said signal SQ.sub.(i-1) by said signal SI.sub.(i); second multiplier means for multiplying said signal SI.sub.(i-1) bysaid signal SQ.sub.(i) ; third multiplier means for obtaining a squareof said signal SI.sub.(i-1) ; fourth multiplier means for obtaining asquare of said signal SQ.sub.(i) ; subtraction means for obtaining adifference between an output signal of said first multiplier means andan output signal of said second multiplier means; adder means for addingan output signal of said third multiplier means and an output signal ofsaid fourth multiplier means; and divider means for dividing one of anoutput signal of said subtraction means and an output signal of saidadder means by the other.
 12. A digital demodulator comprising:firstmeans for producing digital signals Si.sub.(k) and Sq.sub.(k)respectively expressed by equations (79) and (80) from a digital signalS.sub.(i) expressed by an equation (78); second means for producingdigital signals Si'.sub.(k) and Sq'.sub.(k) respectively expressed byequations (81) and (82) from said digital signals Si.sub.(k) andSq.sub.(k) ; third means for producing digital signals SI.sub.(i) andSQ.sub.(i) respectively expressed by equations (83) and (84) from saiddigital signals Si'.sub.(k) and Sq'.sub.(k) ; and fourth means forproducing a digital demodulated signal y.sub.(i) expressed by anequation (85) from said digital signals SI.sub.(i) and SQ.sub.(i) ;

    S.sub.(i) =(A+1)·cos (2·π·fc·t/fs)(78)

where A is an amplitude signal, fc is a carrier frequency, and fs is asampling frequency,

    Si.sub.(k) =(A+1)·sin (2·(2·k-1)·π·Δf+φ)(79)

where k=1, 2, 3, . . . m Δf is a frequency deviation, and φ is a phasedeviation,

    Sq.sub.(k) =(A+1)·cos (4·k·π·Δf+φ)      (80)

    {Si'.sub.(k) }={(A+1)·sin (2·π·Δf+φ), 0, (A+1)·sin (6·π·Δf+φ), 0, . . . ,}    (81)

    {Sq'.sub.(k) }={0, (A+1)·cos (4·π·Δf+φ), 0, (A+1)·sin (8·π·Δf+φ), 0 , . . . ,}   (82)

    SI.sub.(i) =(A+1)·sin (2·π·Δf+φ)(83)

    SQ.sub.(i) =(A+1)·cos (2·π·Δf+φ)(84)

    y.sub.(i) =(A+1).sup.2                                     ( 85).